Tuesday, September 6, 2011

Instruction Issue Buffer Q&A

Today I finally finished the section on instruction issuing.  This took me a while because I had questions which didn't have readily available answers.  Here are the questions I was attempting to find answers to, along with the answers I eventually found (if you have a better answer to any of these questions, please post it in the comments):

If there are no redundant functional units (ex. only a single integer unit and floating point unit) can it still be superscalar?
Yes, superscalar is just the ability to issue instructions to multiple functional units per clock cycle.

With the single queue method, how many instructions can be issued at once?
This depends on the depth of the superscalar architecture.  If the processor is k-way superscalar, then up to k instructions can be issued in one clock cycle.

How does the in-order single queue method avoid artificial data dependencies?
Instructions complete in-order.

Can the single queue method use out of order issuing?
Yes, although register renaming will be required to fix artificial data dependencies.

Why would you want to use the multiple queue method over the single queue method?
The multiple queue method allows you to cut down on the number of data lines, since you know for certain that a queue will never issue an instruction to a functional unit outside of its designated group.  Splitting up the queues also allows you to perform register renaming for a single queue rather than all of them.  This can allow a certain queue to slip ahead of the others to perform tasks ahead of time.  For example, a queue for the load/store unit could make use of renaming in order to load memory ahead of when it is required.

How does the multiple queue method work without renaming?  How does it avoid artificial data dependencies?
In-order issuing is enforced by preventing an instruction from being issued if instructions ahead of it (possibly in other queues) have not been issued yet.

What is the difference between reservation stations and the multiple queue method?
Instruction operands are stored in the reservation station along with the rest of the instruction's information; a queue grabs the operand values out of the register file.  Reservation stations are typically always out-of-order and thus require renaming.

These are various names for the same concept:
  • Functional Unit Buffer
  • Instruction Issue Buffer
  • Issue Window
  • Window of Execution

This is a short list of some of the organizations of a functional unit buffer:
  • Single Instruction Queue
  • Multiple Instruction Queue
  • Reservation Station

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