I finally have an answer to my question! PleasingFungus from the #tigIRC channel on Esper discussed the question with me for two hours straight today and this is the answer I ended up with:
If a scalar (not superscalar) processor has multiple nonredundant
functional units (a single FPU and a single ALU for example) and it
issues an instruction to the FPU at a certain clock tick, could it issue
another instruction to the ALU at the next clock tick so that both the
FPU and the ALU are executing at the same time (lets say that FPU
instructions take longer to execute than ALU instructions)? Or would
that make the processor superscalar?
A processor is only superscalar if its maximum instruction throughput is greater than 1. Because only a single instruction is being issued each clock cycle, the maximum instruction throughput is 1, so the processor is not superscalar. A processor can have multiple pipelines, but if the maximum instruction throughput is equal to or less than 1 the processor is not considered to be superscalar.
Instruction throughput is a measure of the number of instructions which can be processed by the pipeline (committed) per cycle. Because all instructions don't always get through the pipeline in the same amount of time, the "average instruction throughput" can change depending on which instructions were executed. The maximum instruction throughput is a static measurement however, representing the best case scenario.
Even if the instruction pipeline splits into two separate pipelines (one for each functional unit) at the issue stage (or some other point), if only one instruction is dispatched per clock cycle the processor has an instruction throughput less than or equal to 1. Two instructions might complete at the same time (if one functional unit is slower than the other), thus giving the illusion of having an instruction throughput of 2, but it will take at least one cycle to "recover" from this, during which no instructions will complete; so it evens out.
I am still doing some research into this topic, although I currently consider myself to be about 50% finished with the question. I plan on reading the Pipelining: An Overview series at ars technica after working through some example pipelines on paper.