Today I was able to find an answer to the following research question:
Can a processor have out-of-order execution and in-order completion?
Yes; with one pipeline per active instruction. In other words, for every instruction in the active instruction window (every instruction which can be selected for execution) there needs to be a functional unit. This seems a little impractical and I doubt this sort of processor has been used much.
I am currently working out how the various combinations of in-order/out-of-order and scalar/superscalar affect the design of a processor. I have the superscalar combinations figured out, and I am currently working on the scalar combinations.